TODAES 是电子系统设计和自动化领域的一流 ACM 期刊。它出版的创新工作记录了电子系统规范、设计、分析、模拟、测试和评估方面的重大研究和开发进展，强调计算机科学/工程方向。欢迎理论分析和实际解决方案。

ACM Transactions on Design Automation of Electronic Systems is a leading journal in the field of electronic system design and automation. It publishes innovative work that documents significant research and development advancements in the specification, design, analysis, simulation, testing, and evaluation of electronic systems, with an emphasis on the intersection of computer science and engineering. We welcome submissions of theoretical analyses and practical solutions.

《ACM Transactions on Design Automation of Electronic Systems》是电子系统设计与自动化领域的顶尖期刊。该期刊发表的创新研究涵盖了电子系统的规范、设计、分析、模拟、测试和评估等方面的重大进展，强调计算机科学与工程的交叉领域。我们欢迎理论分析和实际解决方案的投稿。

ACM Transactions on Design Automation of Electronic Systems

Tunable analog/RF circuit has emerged as a promising technique to address the significant performance uncertainties caused by process variations. To optimize these tunable circuits after fabrication, most existing post-silicon programming methods are developed by using real-valued performance metrics. However, when measuring a performance of interest on silicon, it is often substantially more expensive to obtain a real-valued measurement than a binary testing outcome (i.e., pass or fail). In this article, we propose a Gaussian Process Classification model to capture the binary performance metrics of tunable analog/RF circuits. Based on these models, post-silicon programming is cast into an optimization problem that can be solved by a novel Bayesian optimization algorithm. Moreover, measurement noises are further incorporated into our proposed post-silicon programming to produce a robust circuit. Two circuit examples demonstrate that the proposed approach can efficiently program tunable circuits with binary performance metrics while other conventional methods are not applicable.

Renjian Pan

Jun Tao

Yangfeng Su

Dian Zhou

Xuan Zeng

Xin Li

Analog/RF Post-silicon Tuning via Bayesian Optimization

通过贝叶斯优化进行模拟/射频硅后调谐

Compute-in-memory (CIM) is an attractive solution to address the “memory wall” challenges for the extensive computation in deep learning hardware accelerators. For custom ASIC design, a specific chip instance is restricted to a specific network during runtime. However, the development cycle of the hardware is normally far behind the emergence of new algorithms. Although some of the reported CIM-based architectures can adapt to different deep neural network (DNN) models, few details about the dataflow or control were disclosed to enable such an assumption. Instruction set architecture (ISA) could support high flexibility, but its complexity would be an obstacle to efficiency. In this article, a runtime reconfigurable design methodology of CIM-based accelerators is proposed to support a class of convolutional neural networks running on one prefabricated chip instance with ASIC-like efficiency. First, several design aspects are investigated: (1) the reconfigurable weight mapping method; (2) the input side of data transmission, mainly about the weight reloading; and (3) the output side of data processing, mainly about the reconfigurable accumulation. Then, a system-level performance benchmark is performed for the inference of different DNN models, such as VGG-8 on a CIFAR-10 dataset and AlexNet GoogLeNet, ResNet-18, and DenseNet-121 on an ImageNet dataset to measure the trade-offs between runtime reconfigurability, chip area, memory utilization, throughput, and energy efficiency.

Anni Lu

Xiaochen Peng

Yandong Luo

Shanshi Huang

Shimeng Yu

A Runtime Reconfigurable Design of Compute-in-Memory–Based Hardware Accelerator for Deep Learning Inference

基于存内计算的深度学习推理硬件加速器的运行时可重构设计

With the down-scaling of CMOS technology, the design complexity of very large-scale integrated is increasing. Although the application of machine learning (ML) techniques in electronic design automation (EDA) can trace its history back to the 1990s, the recent breakthrough of ML and the increasing complexity of EDA tasks have aroused more interest in incorporating ML to solve EDA tasks. In this article, we present a comprehensive review of existing ML for EDA studies, organized following the EDA hierarchy.

Guyue Huang

Jingbo Hu

Yifan He

Jialong Liu

Mingyuan Ma

Zhaoyang Shen

Juejian Wu

Yuanfan Xu

Hengrui Zhang

Kai Zhong

Xuefei Ning

Yuzhe Ma

Haoyu Yang

Bei Yu

Huazhong Yang

Yu Wang

ACM Trans. Des. Autom. Electron. Syst.

Machine Learning for Electronic Design Automation: A Survey

电子设计自动化中的机器学习：综述

Partially dynamic reconfiguration (PDR) technology can accelerate the reconfiguration process and overcome hardware resource constraints when facing the challenge of high performance with respect to applications and resources constraints on field-programmable gate arrays (FPGAs). On FPGAs with PDR technology, the available on-chip Block RAM (BRAM) resources may not satisfy the memory requirements for all data. If we reserve more BRAM resources, then the total area of the dynamically reconfigurable region (DRR) that is used for calculation will decrease, with a reduction in system performance. We propose a memory-aware optimization framework to search for the optimal solution considering partitioning, scheduling, and floorplanning, where we make a tradeoff between performance and on-chip memory resources utilization. We then propose methods for memory allocation: An ILP model and a heuristic algorithm are provided to determine the minimum memory requirements and the number of corresponding memory blocks for data, as well as to determine whether the memory block with its stored data is assigned on-chip or off-chip by formulating the problem into a 0-1 knapsack problem and solving it using dynamic programming. Experimental results show that the memory-aware optimization framework and methods of memory allocation can increase the amount of on-chip data access to 29.65% of the total data volume with guaranteed performance.

Bo Ding

Jinglei Huang

Qi Xu

Junpeng Wang

Song Chen

Yi Kang

Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems

面向部分动态可重构系统的记忆感知分区、调度与布局规划

Multi-Scalar Multiplication (MSM) is a computationally intensive task that operates on elliptic curves based onGF(P). It is commonly used in zero-knowledge proof (ZKP), where it accounts for a significant portion of the computation time required for proof generation. In this article, we present PriorMSM, an efficient acceleration architecture for MSM. We propose a Priority-Based Scheduling Mechanism (PBSM) based on a multi-FIFO and multi-bank architecture to accelerate the implementation of MSM. By increasing the pairing success rate of internal points, PBSM reduces the number of bubbles in the pipeline of point addition (PADD), consequently improving the data throughput of the pipeline. We also introduce an advanced parallel bucket aggregation algorithm, leveraging PADD’s fully pipelined characteristics to significantly accelerate the implementation of bucket aggregation. We perform a sensitivity analysis on the crucial parameter of window size in MSM. The results indicate that the window size of the MSM significantly impacts its latency. Area-Time Product (ATP) metric is introduced to guide the selection of the optimal window size, balancing the performance and cost for practical applications of subsequent MSM implementations. PriorMSM is evaluated using the TSMC 28 nm process. It achieves a maximum speedup of 10.9× compared to the previous custom hardware implementations and a maximum speedup of 3.9× compared to the GPU implementations.

Changxu Liu

Hao Zhou

Patrick Dai

Li Shang

Fan Yang

PriorMSM: An Efficient Acceleration Architecture for Multi-Scalar Multiplication

PriorMSM: 一种高效的多标量乘法加速架构

With increasing transistor density, modern heterogeneous embedded processors often exhibit high temperature gradients due to complex application scheduling scenarios which may have missed design considerations. In many use cases, off-chip ”active” cooling solutions are considered prohibitive in such reduced form factors. Core frequency throttling by existing dynamic thermal management techniques often compromises the Quality-of-Service (QoS) and violates real-time deadlines. This necessitates the adoption of intelligent resource management that simultaneously manages both thermal and latency performance. Coupled with the complexity of modern heterogeneous multi-cores, the periodic application updates that cater to ever-changing user requirements often render model-driven thermal-aware resource allocation approaches unsuitable for heterogeneous multi-core systems. For such application-architecture scenarios, we propose a novel self-learning based resource manager using Reinforcement Learning that intelligently manipulates core frequencies and task set mappings to fulfil thermal and latency objectives. Our framework employs a data-driven system modeling technique using Gaussian Process Regression to enable efficient offline training of this learning-based resource manager to avoid challenges associated with initial online training. We evaluate the approach on a heterogeneous embedded CPU-GPU platform with real workloads and observe a significant reduction in peak operating temperature when compared to the default onboard frequency governor as well as other learning-based state-of-the-art approaches.

Srijeeta Maity

Anirban Majumder

Rudrajyoti Roy

Ashish Hota

Soumyajit Dey

Harnessing Machine Learning in Dynamic Thermal Management in Embedded CPU-GPU Platforms

在嵌入式CPU-GPU平台中利用机器学习进行动态热管理

Approximate computing emerges as a viable solution to enhance energy efficiency in applications sensitive to human perception, particularly on edge devices. This work introduces a novel piece-wise approximate floating-point divider that boasts resource efficiency and runtime configurability. Our method leverages a piece-wise approximation algorithm for computing 1/ y by exploiting powers of 2, complemented by an error compensation technique grounded in thorough mathematical analysis. This approach facilitates the realization of a reciprocal-based floating-point divider devoid of multipliers, which not only mitigates hardware resource consumption but also reduces latency. Additionally, we unveil a multi-level runtime configurable hardware architecture that significantly improves flexibility across diverse application contexts. Compared to the existing state-of-the-art approximate dividers and truncated exact dividers, our proposed solution achieves a superior compromise between precision and resource efficiency. Application-level evaluations reveal that our design provides over 87.7% energy saving, while maintaining a negligible impact on output quality.

Chenyi Wen

Haonan Du

Jiayi Wang

Zhengrui Chen

Li Zhang

Qi Sun

Cheng Zhuo

PACE: A Piece-Wise Approximate Floating-Point Divider with Runtime Configurability and High Energy Efficiency

PACE：一种具有运行时可配置性和高能效的分段近似浮点除法器

Digital SRAM-based CIM architectures must balance three critical factors: quantized neural network bitwidth, accuracy loss, and computational efficiency, each crucial to optimizing performance and efficiency. In Domain Specific Accelerators (DSAs), flexible and specific hardware design, when incorporated with tailored Power-of-2 (P-2) quantization schemes, addresses this issue. However, in CIMs, the absence of flexible and specific hardware to support dynamic switching between general and tailored quantization schemes hinders the adoption of efficient quantization methods. In this paper, we propose the I n-situ S hift O peration based Acc elerator ( ISOAcc ) for efficient SRAM-based multiplication. The key idea is to introduce transmission gates near the SRAM array to enable the selection of bits from either the same or the neighbor line when data flows from one row to another. This functionally equals a shift operation. By configuring the transmission gates array in a cascade manner, ISOAcc can support 0 to 15-bit shift with a negligible overhead. The ISOAcc can directly leverage P-2 quantization schemes in hardware, thereby greatly reducing multiplication cycles. We have chosen five well-known neural networks to evaluate ISOAcc. The evaluations show that ISOAcc achieves an average performance improvement of 3.24 × and an energy reduction of 75%, compared to the state-of-the-art (SOTA) SRAM-based CIM design, Bit-Parallel.

Gaoyang Zhao

Junzhong Shen

Rongzhen Lin

Hua Li

Yaohua Wang

ISOAcc: In-situ Shift Operation-based Accelerator For Efficient in-SRAM Multiplication

ISOAcc: 基于原位移位操作的高效SRAM内乘法加速器

Graphics Processing Units (GPUs) are becoming widespread, even in safety-critical applications. In that case, it is imperative to guarantee that the probability of producing critical failures due to hardware faults is lower than a given threshold. To detect possible permanent hardware faults as soon as they appear during the operational phase (e.g., due to aging), Software Test Libraries (STLs) have gained significant traction as a widely adopted test solution due to their effectiveness in terms of fault detection capabilities, test application time, and flexibility. However, a major drawback of this solution is the lack of automation in the STL generation phase. As a result, high manual labor is required for their generation. This becomes even more arduous in complex architectures that require in-depth knowledge to cover hard-to-test faults. In this paper, we introduce a methodology based on Bounded Model Checking to support the generation and improvement of stuck-at-oriented STLs for hard-to-test units in GPUs, showing that we can enhance the test coverage achieved by pre-existing STLs while also identifying a set of functionally untestable faults. To experimentally validate the proposed method’s effectiveness, we use the FlexGripPlus GPU model to target two hard-to-test units, one medium to low complexity sub-unit and one high complexity sub-unit, as study cases. For both units, we had pre-existing STLs written for the stuck-at model. Resorting to the proposed method, the STLs’ test coverage was increased by 9.57% and 2.19%, respectively. In addition, the method also identified a significant number of functionally untestable faults.

Nikolaos Deligiannis

Tobias Faller

Josie Esteban Rodriguez Condia

Riccardo Cantoro

Bernd Becker

Matteo Sonza Reorda

Enhancing the Effectiveness of STLs for GPUs via Bounded Model Checking

通过有界模型检验提升GPU的STL有效性

Rapid growth in Deep Neural Network (DNN) workloads has increased the energy footprint of the Artificial Intelligence (AI) computing realm. For optimum energy efficiency, we propose operating a DNN hardware in the Low-Power Computing (LPC) region. However, operating at LPC causes increased delay sensitivity to Process Variation (PV). Delay faults are an intriguing consequence of PV. In this paper, we demonstrate the vulnerability of DNNs to delay variations, substantially lowering the prediction accuracy. To overcome delay faults, we present STRIVE—a post-fabrication fault detection and reactive error reduction technique. We also introduce a time-borrow correction technique to ensure error-free DNN computation.

Noel Daniel Gundi

Sanghamitra Roy

Koushik Chakraborty

STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience

STRIVE：为低功耗张量处理单元赋能故障检测与错误韧性

Abbreviation	ACM Trans. Des. Autom. Electron. Syst.
Journal Impact	2.23
Quartiles(Global)	COMPUTER SCIENCE, SOFTWARE ENGINEERING(Q2)

ISSN	1084-4309, 1557-7309
h-index	56

Publication Information	Publisher: Association for Computing Machinery (ACM)，Publishing cycle: Quarterly，Journal Type: journal，Open Access Journals: No
Basic data	Year of publication: 1996，Proportion of original research papers: 100.00%，Self Citation Rate:4.50%， Gold OA Rate: 2.80%
Average review cycle	网友分享经验：较慢,6-12周
Average recruitment ratio	网友分享经验：容易

ACM Transactions on Design Automation of Electronic Systems

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