Hardware Obfuscation Based Watermarking Technique for IPR Ownership Identification

2023-7-3

Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation

2023-5-23

International Journal of Reconfigurable Computing

2022-9-19

A Methodology for an FPGA Implementation of a Programmable Logic Controller to Control an Atomic Layer Deposition System

2022-5-6

A Decision-Making Method Providing Sustainability to FPGA-Based SoCs by Run-Time Structural Adaptation to Mode of Operation, Power Budget, and Die Temperature Variations

2021-9-1

A Service-Oriented Component-Based Framework for Dynamic Reconfiguration Modeling Targeting SystemC/TLM

2021-8-3

A Method for Run-Time Prediction of On-Chip Thermal Conditions in Dynamically Reconfigurable SOPCs

2021-1-7

FPGAs for Domain Experts

2020-10-16

FPGA Implementation of A<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="M1"><mml:msup><mml:mrow /><mml:mrow><mml:mi>∗</mml:mi></mml:mrow></mml:msup></mml:math> Algorithm for Real-Time Path Planning

2020-8-17

Dynamic Reliability Management for FPGA-Based Systems

2020-6-13

SIFO: Secure Computational Infrastructure Using FPGA Overlays

2019-12-6

From FPGA to Support Cloud to Cloud of FPGA: State of the Art

2019-12-5

Automatic Pipelining and Vectorization of Scientific Code for FPGAs

2019-11-18

ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures

2019-11-14

Dimension Reduction Using Quantum Wavelet Transform on a High-Performance Reconfigurable Computer

2019-11-11

Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)

2019-11-3

An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories Only: Design and Benchmarking with Intel Movidius Neural Compute Stick

2019-10-22

Implementing and Evaluating an Heterogeneous, Scalable, Tridiagonal Linear System Solver with OpenCL to Target FPGAs, GPUs, and CPUs

2019-10-13

A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor

2019-9-22

FPGA Implementation of an Improved Reconfigurable FSMIM Architecture Using Logarithmic Barrier Function Based Gradient Descent Approach

2019-4-1

Exposing End-to-End Delay in Software-Defined Networking

2019-3-4

AsyncBTree: Revisiting Binary Tree Topology for Efficient FPGA-Based NoC Implementation

2019-2-20

On a Real-Time Blind Signal Separation Noise Reduction System

2018-12-4

Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal

2018-8-6

Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions

2018-7-10

Design of FPGA-Based Accelerator for Convolutional Neural Network under Heterogeneous Computing Framework with OpenCL

2018-7-2

Corrigendum to “An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization”

2018-6-21

Corrigendum to “Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm”

2018-4-1

Corrigendum to “PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability”

2018-3-20

RP-Ring: A Heterogeneous Multi-FPGA Accelerator

2018-1-1

Reconfigurable Network Stream Processing on Virtualized FPGA Resources

2018-1-1

Exploiting Partial Reconfiguration through PCIe for a Microphone Array Network Emulator

2018-1-1

Toward the Implementation of an ASIC-Like System on FPGA for Real-Time Video Processing with Power Reduction

2018-1-1

FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method

2018-1-1

Real-Time Control System for Improved Precision and Throughput in an Ultrafast Carbon Fiber Placement Robot Using a SoC FPGA Extended Processing Platform

2017-1-1

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

2017-1-1

Efficient Realization of BCD Multipliers Using FPGAs

2017-1-1

Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

2017-1-1

OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions

2017-1-1

Challenges in Clock Synchronization for On-Site Coding Digital Beamformer

2017-1-1

FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

2017-1-1

Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection

2017-1-1

Software-Defined Radio FPGA Cores: Building towards a Domain-Specific Language

2017-1-1

On-Chip Reconfigurable Hardware Accelerators for Popcount Computations

2016-3-1

An Efficient FPGA Implementation of Optimized Anisotropic Diffusion Filtering of Images

2016-1-1

An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems

2016-1-1

An Accelerating Solution for<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="M1"><mml:mrow><mml:mi>N</mml:mi></mml:mrow></mml:math>-Body MOND Simulation with FPGA-SoC

2016-1-1

FPGA-Based Real-Time Moving Target Detection System for Unmanned Aerial Vehicle Application

2016-1-1

On-Chip Reconfigurable Hardware Accelerators for Popcount Computations

2016-1-1

An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture

2016-1-1