ACM Transactions on Reconfigurable Technology and Systems
Abbreviation | ACM Trans. Reconfigurable Technol. Syst. |
Journal Impact | 3.14 |
Quartiles(Global) | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE(Q2) |
ISSN | 1936-7406, 1936-7414 |
h-index | 35 |
ACM Transactions on Reconfigurable Technology and Systems (TRETS) is a premier journal dedicated to research on reconfigurable systems and their underlying technologies. Unlike other journals that may focus on specific aspects of reconfigurable technology or systems, TRETS covers a broader range of topics. Suitable subjects for TRETS include all levels of abstraction for reconfigurable systems and all aspects of reconfigurable technology, including platforms, programming environments, and applications that support the successful use of these systems in computing or other applications. Specifically, TRETS focuses on the following areas: hardware and system architecture of reconfigurable platforms; programming environments for reconfigurable systems, especially those designed to enhance programmer productivity; programming languages and compilers for reconfigurable systems; logic synthesis and related tools as they pertain to reconfigurable systems; and foundational technologies for developing successful applications (currently primarily FPGA technology, but research on future technologies is also appropriate for TRETS). When considering whether a paper is suitable for TRETS, the most important question is whether reconfigurability is critical to its success. If the context is appropriate, topics such as architecture, programming languages, compilers and environments, logic synthesis, and high-performance applications are all suitable. For example, while an embedded application architecture that happens to use FPGA may not be suitable for TRETS, an architecture where the reconfigurability of the FPGA is an inherent part of the specification (possibly due to the need for reuse across multiple applications) would be appropriate for TRETS.
HomepagePublication Information | Publisher: Association for Computing Machinery (ACM),Publishing cycle: ,Journal Type: journal,Open Access Journals: No |
Basic data | Year of publication: 2008,Proportion of original research papers: 100.00%,Self Citation Rate:9.70%, Gold OA Rate: 3.97% |
Average review cycle | 网友分享经验:>12周,或约稿 |
Average recruitment ratio | 网友分享经验:容易 |
Journal Citation Format
Those examples are references to articles in scholarly journals and how they are supposed to appear in your bibliography.
Not all journals organize their published articles in volumes and issues, so these fields are optional. Some electronic journals do not provide a page range, but instead list an article identifier. In a case like this it's safe to use the article identifier instead of the page range.
A journal article with 1 author
A journal article with 2 authors
A journal article with 3 authors
A journal article with 5 or more authors
Books Citation Format
Here are examples of references for authored and edited books.
Thesis Citation Format
Web sites Citation Format
Sometimes references to web sites should appear directly in the text rather than in the bibliography.
Patent Citation Format
Staying up late manually editing references? ivySCI automatically matches journals and helps you generate references with a single click.
Click the button below to start a free trial!
Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow
2023-4-2
FPGA-based Deep Learning Inference Accelerators: Where Are We Standing?
2023-9-4
COFFE 2
2019-4-5
Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing With FPGAs
2018-6-30
On the Malicious Potential of Xilinx’s Internal Configuration Access Port (ICAP)
2023-11-17
Accelerating In-memory Database Functionality with FPGAs
2024-12-18
FPGA-based Block Minifloat Training Accelerator for a Time Series Prediction Network
2024-12-6
Compressing Neural Networks Using Learnable 1-D Non-Linear Functions
2024-12-3
DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination
2024-12-2
A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis
2024-11-26