CCF Transactions on High Performance Computing

Yu Pan

Xiaotao Jia

Zhen Cheng

Peng Ouyang

Xueyan Wang

Jianlei Yang

Weisheng Zhao

An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing

基于STT-MRAM的可重构计算存储架构用于通用计算

Abstract Merge sort as a divide-sort-merge paradigm has been widely applied in computer science fields. As modern reduced instruction set computing architectures like the fifth generation (RISC-V) regard multiple registers as a vector register group for wide instruction parallelism, optimizing merge sort with this vectorized property is becoming increasingly common. In this paper, we overhaul the divide-sort-merge paradigm, from its register-level sort to the cache-aware merge, to develop a fine-grained RISC-V vectorized merge sort (RVMS). From the register-level view, the inline vectorized transpose instruction is missed in RISC-V, so implementing it efficiently is non-trivial. Besides, the vectorized comparisons do not always work well in the merging networks. Both issues primarily stem from the expensive data shuffle instruction. To bypass it, RVMS strides to take register data as the proxy of data shuffle to accelerate the transpose operation, and meanwhile replaces vectorized comparisons with scalar cousin for more light real value swap. On the other hand, as cache-aware merge makes larger data merge in the cache, most merge schemes have two drawbacks: the in-cache merge usually has low cache utilization, while the out-of-cache merging network remains an ineffectively symmetric structure. To this end, we propose the half-merge scheme to employ the auxiliary space of in-place merge to halve the footprint of naïve merge sort, and meanwhile copy one sequence to this space to avoid the former data exchange. Furthermore, an asymmetric merging network is developed to adapt to two different input sizes. Experiments on the RISC-V processor SG2042 show that four fine-grained optimization schemes including register strided transpose, hybrid merging network, half-merge strategy, and asymmetric merging network, improve performance by 4.05%, 19.88%, 12.23%, and 11.04% respectively. Importantly, the overall performance is 1.34x faster than the parallel sorting in the Boost C++ library, and 1.85x faster than std::sort.

Jin Zhang

Jincheng Zhou

Xiang Zhang

Di Ma

Chunye Gong

Fine-grained vectorized merge sorting on RISC-V: from register to cache

基于RISC-V的细粒度向量化归并排序：从寄存器到缓存

Muchun Peng

Qinglin Wang

Yuechao Liang

Weihao Guo

Shun Yang

Yaling Liang

Yongzhen Shi

Ligang Cao

Jie Liu

GreenB+Tree: an energy-efficient B+tree for MIMD architectures

GreenB+Tree：面向MIMD架构的节能B+树

Jianfeng Liu

Jianbin Fang

Ting Wang

Jing Xie

Chun Huang

Zheng Wang

Efficient compiler optimization by modeling passes dependence

通过建模优化过程依赖实现高效编译器优化

Bao Zhenshan

Wang Mengyuan

Wei Bai

Zhang Wenbo

Multi-index federated aggregation algorithm based on trusted verification

基于可信验证的多指标联邦聚合算法

Abstract We present swRender , a new parallel rendering pipeline based on the new Sunway many-core architecture (SW26010P) for the Monte Carlo path-tracing algorithm. Previous parallel rendering schemes are unsuitable for our task due to issues such as vast differences in hardware architectures and bottlenecks in I/O communication efficiency. To that end, we create a new two-level parallel tile rendering framework to fully utilize the Sunway computing resources, a practical tile-grouping load-balancing method to maintain the framework’s stability, and a novel many-core acceleration optimization to improve the rendering performance at the pixel level. Our method achieves (1) an average speedup of 16x in multiple benchmarks when compared to the baseline path-tracing model on the Sunway architecture, and (2) an average speedup of 2x when compared to state-of-the-art CPU, co-processor, and GPU-based parallel rendering approaches. Moreover, we scale swRender to run on 15 million cores and obtain high scalable parallel efficiency of 92%.

Xinjie Wang

Guanghao Ma

Jiaying Song

Mingyao Geng

Wenhui Hu

Xi Duan

Zhigang Wang

Jiali Xu

Xiaogang Jin

Fang Li

Dexun Chen

Maoxue Yu

Heterogeneous many-core optimization for Monte Carlo path-tracing on new generation Sunway HPC system

新一代神威高性能计算系统上蒙特卡罗路径追踪的异构众核优化

Abbreviation	CCF Trans. HPC
Journal Impact	1.12
Quartiles(Global)	COMPUTER SCIENCE, THEORY & METHODS(Q3)

Publication Information	Publisher: Springer，Publishing cycle: ，Journal Type: journal，Open Access Journals: No
Basic data	Year of publication: 2019，Proportion of original research papers: 83.72%，Self Citation Rate:15.40%， Gold OA Rate: 4.63%

CCF Transactions on High Performance Computing

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Share Submission Experience

An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing

Fine-grained vectorized merge sorting on RISC-V: from register to cache

GreenB+Tree: an energy-efficient B+tree for MIMD architectures

Efficient compiler optimization by modeling passes dependence

Multi-index federated aggregation algorithm based on trusted verification

Heterogeneous many-core optimization for Monte Carlo path-tracing on new generation Sunway HPC system

Multi-index federated aggregation algorithm based on trusted verification

Fine-grained vectorized merge sorting on RISC-V: from register to cache

GreenB+Tree: an energy-efficient B+tree for MIMD architectures

Efficient compiler optimization by modeling passes dependence

ISSN	2524-4922, 2524-4930
h-index	9